cystech electronics corp. spec. no. : c0 11 n3 issued date : 2018.07.27 revised date : page no. : 1/9 mt a025n03ksn3 cystek product specification 30v n-channel enhancement mode mosfet mt a025 n0 3ksn3 features ? simple drive requirement ? small package outline ? esd protected gate, hbm R 2kv ? pb -free lead plating and halogen-free package symbol outline ordering information device package shipping mt a 025 n0 3 ksn3 -0- t1 -g s ot -23 (pb-free lead plating and halogen-free package) 3000 pcs / tape & reel sot- 23 mt a0 25 n03 ks n3 g gate s source d drain bv dss 3 0v i d @ t a =25 ? c, v gs =10v 5 .3 a r dson @v gs =10v, i d =6 .2 a 22.4m (typ) r dson @v gs =4.5v, i d =5a 2 4. 5m (typ) r dson @v gs =2.5v, i d =3a 31.9m (typ) environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t1 : 3000 pcs / tape & reel,7 reel product rank, zero for no rank products product name d g s
cystech electronics corp. spec. no. : c0 11 n3 issued date : 2018.07.27 revised date : page no. : 2/9 mt a025n03ksn3 cystek product specification absolute maximum ratings (ta=25 ? c) parameter symbol limits unit drain-source voltage v ds 30 v gate-source voltage v gs 12 continuous drain current @ t a =25 ? c, v gs =10 v (note 3) i d 5.3 a continuous drain current @ t a =70 ? c, v gs =10 v (note 3) 4.2 pulsed drain current (notes 1, 2) i dm 30 ma ximum power dissipation@ t a =25 (note 3) p d 1.38 w maximum power dissipation@ t a =70 (note 3) 0.88 operating junction and storage temperature range tj ; tstg -55~+150 ? c note : 1. pulse width limited by maximum junction temperature. 2. pulse width 300 s, duty cycle 2%. 3. surface mounted on 1 in2 copper pad of fr -4 board; 270 ? c/w when mounted on minimum copper pad thermal performance parameter symbol limit unit thermal resistance, junction- to -ambient, max r ja 90 ? c /w th ermal resistance, junction- to -case, max r j c 50 note : surface mounted on 1 in2 copper pad of fr -4 board; 270 ? c/w when mounted on minimum copper pad electrical characteristics (tj=25 ? c, unless otherwise noted ) symbol min. typ. max. unit test conditions static bv dss 30 - - v v gs =0v, i d =250 a v gs(th) 0.6 - 1.3 v ds =v gs , i d =250 a i gss - - 15 a v gs = 12v, v ds =0v i dss - - 1 v ds =24v, v gs =0v - - 10 v ds =24v, v gs =0v (tj=85 ? c) *r ds(on) - 22.4 30 m ? v gs =10v, i d =6.2a - 24.5 35 v gs =4.5v, i d =5a - 31.9 50 v gs =2.5v, i d =3a *g fs - 5.8 - s v ds =10v, i d =3a dynamic ciss - 477 - pf v ds =25v, v gs =0 v, f=1mhz coss - 46 - crss - 3.8 - t d(on) - 303 - ns v ds =15v, i d =6.2a, v gs =10v, r g =1 t r - 461 - t d(off) - 4304 - t f - 7518 -
cystech electronics corp. spec. no. : c0 11 n3 issued date : 2018.07.27 revised date : page no. : 3/9 mt a025n03ksn3 cystek product specification qg - 20.2 - nc v ds =15v, i d =6.2a, v gs =10v qgs - 0.4 - qgd - 2.0 - source-drain diode *i s - - 1 a *i sm - - 4 *v sd - 0.7 1.1 v v gs =0v, i f =1a *trr - 991 - ns i f =6.2a, v gs =0v, di f /dt=100a/ s *qrr - 5.36 - c *pulse test : pulse width ? 300s, duty cycle ? 2% recommended soldering footprint
cystech electronics corp. spec. no. : c0 11 n3 issued date : 2018.07.27 revised date : page no. : 4/9 mt a025n03ksn3 cystek product specification typical characteristics typical output characteristics 0 3 6 9 12 15 18 21 24 27 30 0 1 2 3 4 5 v ds , drain-source voltage(v) i d , drain current (a) 10v,9v,8v,7v,6v,5v,4v,3.5v,3v v gs =1.5v 2v 2.5v brekdown voltage vs junction temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 , jc eeaec bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain curre nt 1 10 100 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state eace v gs =2.5v 3.0v 4.5v 10 v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 0 4 8 12 16 20 i dr , reverse drain current(a) v sd , source-drain voltage(v) =c =c v gs =0v static drain-source on-state resistance vs gate-sou rce voltage 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 v gs , gate-source voltage(v) r ds(on) , static drain-source on- ae eace i d =6.2 i d =3a drain-source on-state resistance vs junction tempea rture 0 0.4 0.8 1.2 1.6 2 2.4 -75 -50 -25 0 25 50 75 100 125 150 175 , jc eeaec r ds(on) , normalized static drain- source on-state resistance v gs =4.5v, i d =5a r ds(on) @=c y v gs =10v, i d =6.2a r ds(on) @=c y
cystech electronics corp. spec. no. : c0 11 n3 issued date : 2018.07.27 revised date : page no. : 5/9 mt a025n03ksn3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 1 10 100 1000 0 5 10 15 20 25 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 , jc eeaec v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) a=c pulsed v ds =10v gate charge characteristics 0 2 4 6 8 10 0 4 8 12 16 20 24 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =6.2a v ds =15v maximum safe operating area 0.01 0.1 1 10 100 0.01 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) t a =c, =c v gs =10v, r ja =c single pulse dc 100ms r dson limited 100 s 1ms 1s 10ms maximum drain current vs junction temperature 0 1 2 3 4 5 6 7 25 50 75 100 125 150 175 , jc eeaec i d , maxim um drain current(a) t a =c, gs =10v, r ja =c
cystech electronics corp. spec. no. : c0 11 n3 issued date : 2018.07.27 revised date : page no. : 6/9 mt a025n03ksn3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 3 6 9 12 15 18 21 24 27 30 0 1 2 3 4 5 v gs , gate-source voltage(v) i d , drain current(a) v ds =5v single pulse power rating, junction to ambient (note on page 2) 0 10 20 30 40 50 0.001 0.01 0.1 1 10 100 1000 pulse width(s) power (w) t j(max) =c t a =c r ja =c transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =90c/w
cystech electronics corp. spec. no. : c0 11 n3 issued date : 2018.07.27 revised date : page no. : 7/9 mt a025n03ksn3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c0 11 n3 issued date : 2018.07.27 revised date : page no. : 8/9 mt a025n03ksn3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb -free devices 260 +0/- 5 ? c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn -pb eutectic assembly pb -free assembly average ramp-up rate (tsmax to tp) 3 ? c/second max. 3 ? c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 ? c 150 ? c 60 -120 seconds 150 ? c 200 ? c 60 -180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 ? c 60 -150 seconds 217 ? c 60 -150 seconds peak temperature(t p ) 240 +0/- 5 ? c 260 +0/- 5 ? c time within 5 ? c of actual peak temperature(tp) 10 -30 seconds 20 -40 seconds ramp down rate 6 ? c/second max. 6 ? c/second max. time 25 ? c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c0 11 n3 issued date : 2018.07.27 revised date : page no. : 9/9 mt a025n03ksn3 cystek product specification sot-23 dimension *: typical dim inches millimeters dim inches millimeters min. max. min. max. min. max. min. max. a 0.1102 0.1204 2.80 3.04 j 0.0032 0.0079 0.08 0.20 b 0.0472 0.0 551 1.20 1. 40 k 0.0118 0.0266 0.30 0.67 c 0.0335 0.0512 0.89 1.30 l 0.0335 0.0453 0.85 1.15 d 0.0118 0.0197 0.30 0.50 s 0.0830 0.1 004 2.10 2. 55 g 0.0669 0.0910 1.70 2.30 v 0.0098 0.0256 0.25 0.65 h 0.0000 0.0040 0.00 0.10 l1 0.0118 0.0197 0.30 0.50 notes: 1. controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please contact your local c ystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v -0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. marking: te style: pin 1.gate 2.source 3.drain 3-lead sot-23 plastic surface mounted package cystek package code: n3 a tnk xx de vice code date code
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